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User Testbench
Files Used in the Verification Testbench
Table 8-2 lists all the VHDL source files used in the verification testbench and gives a description of their functions. All
source files are provided with the RTL release. With the Evaluation release, only some of the source files are provided.
All others are pre-compiled into the CorePCIF simulation library.
Table 8-2 · Verification Testbench Source Files
File
tb_verif.vhd
coreconfig.vhd
pci_monitor.vhd
Supplied
Yes
Yes
RTL only
Function
Top level of testbench. Creates a PCI bus and instantiates all the devices connected to the bus.
VHDL package that is used to configure the number of cores and the parameter settings for each of
the cores. By default, 12 cores are configured, allowing multiple core implementations to be tested at
the same time.
PCI bus monitor that monitors PCI activity, looking for illegal activity. Also capable of tracing and
displaying PCI activity.
pci_target.vhd
pci_arbiter.vhd
RTL only PCI Target used to generate error conditions when testing the DMA function.
RTL only PCI arbiter that supports up to 16 Masters used in the testbench.
test_master.vhd
fast_master.vhd
RTL only
RTL only
PCI Master function used by the testbench to carry out PCI cycles. Also contains the main procedural
testbench and user command entry code. It calls the tests provided in the tests.vhd package.
Second PCI Master function used by the testbench to carry out PCI cycles. This Master is capable of
performing PCI transactions at a very fast rate.
tests.vhd
RTL only VHDL package that contains all the procedures used for performing the tests
usertests.vhd
RTL only
VHDL package that contains some basic test routines that can be used as templates for adding
additional tests if required
tb_package.vhd
backend.vhd
RTL only VHDL package that defines all the types and low-level function calls used in the testbench
This backend interface logic implements each of the required backend memory blocks using
RTL only bendmem.vhd , and provides control logic to access the backend interface. It also allows the testbench to
control and monitor the backend interface.
bendmem.vhd
waveforms.vhd
waveform.vhd
RTL only
RTL only
RTL only
Implements the actual backend memory block for each configured BAR. It can be configured to
operate as a FIFO or as memory.
VHDL package that contains all the procedures used for generating the waveforms shown in this
handbook
Monitors the PCI bus and retimes the signals for output to a VCD file for generation of the
waveforms shown in this handbook.
tb_components.vhd
textio.vhd
misc.vhd
RTL only VHDL package that declares the components used in the testbench
RTL only VHDL package that provides the printf function used in the testbench
RTL only VHDL package that provides some very low-level type definitions and functions
User Testbench
The user testbenches are intended to act as a starting point for creating a simulation environment for the end-user
circuit, and are provided in both VHDL and Verilog. The testbench structure and tests carried out are identical for the
VHDL and Verilog testbenches.
v4.0
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相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
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CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
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相关代理商/技术参数
COREPCIF-RMFL 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPRO LEDBULB 10.5-60W B 制造商:Philips Lumileds 功能描述:
COREPRO LEDBULB 10.5-60W E 制造商:Philips Lumileds 功能描述: